The present invention relates generally to reducing power consumption in a processor, and more specifically, to reducing power consumption due to cache accesses in a processor.
Processors generally include one or more cache memories to allow faster access to frequently used instructions and data. Commonly, such caches include both an instruction cache and a data cache. A cache normally includes a tag array containing the address tags of cached information and a data array containing the cached information. Each time data is fetched from the cache, power is consumed.
The presence or absence of instructions and/or data in a processor cache memory has a significant impact on the processor performance as the execution speed of the processor decreases dramatically if instructions and/or data have to be fetched from the main memory. Accordingly, even though only a small number of cache lines are required to execute the majority of instructions required by a software program within a processor, instruction caches are typically configured to be multi-set associative to reduce the amount of cache misses.
In general, the multi-set associativity of the cache increases the power consumption of the cache because the multiple sets of the cache are typically accessed in parallel to increase the performance, by reducing the access latency, of multi-set associative caches, even though the desired instruction or data is only located in one of the sets. By simultaneously accessing each of the cache sets, significant power is wasted by unnecessarily accessing cache sets that do not contain the desired instruction or data. As more and more processing cores are placed on a chip, the amount of performance throughput per watt continues to increase and the power associated with cache associativity becomes more and more expensive.